AI in Space Applications: Electronic Design Challenges
Thanks to its multi-core processor architecture, comprised of four 64-bit Arm® Cortex® A72 cores, it can deliver 30k DMIPs of processing performance. Other functionality incorporated into this device includes a highly effective DDR4 memory controller with embedded 8-bit error corrected code (ECC) to mitigate the threat of data corruption, as well as a 2MB L2 cache that attends to all of its processor cores.